Method for manufacturing complementary insulated gate field effect transistors

ABSTRACT

Method for manufacturing .Iadd.semiconductor devices including, e.g., .Iaddend.complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using .Iadd.an oxidation-resistive material, e.g. .Iaddend.a silicon nitride layer.Iadd., .Iaddend.as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturingcomplementary insulated gate field effect transistors (hereinafterreferred to as CMIS FET's) having a field oxide layer of LOCOS (localoxidation of silicon) structure, and more particularly to a method formanufacturing a semiconductor integrated circuit device comprising suchtransistors.

2. Description of the Prior Art

In prior art CMIS FET's of the LOCOS structure, a power supply voltagetherefor is determined by a threshold voltage V_(th) of an active regionwhich is a channel region immediately beneath a gate electrode and athreshold voltage V_(th) of a parastic MOS FET in a field oxide layerregion. Accordingly, when it is desired to raise the power supplyvoltage for the CMIS FET's, it is necessary to change the impurityconcentration of a substrate and the impurity concentration of a welllayer which is of opposite conductivity type to that of the substrate.Namely, the threshold voltage V_(th) is defined by ##EQU1## where Q_(b)is a charge in a bulk, Q_(ss) is surface state and oxide charge, andC_(g) is the capacitance of the gate. A simple way to control thethreshold voltage V_(th) defined by the equation (1) is to controlQ_(b). That is, Q_(b) is related to the impurity concentration of thesubstrate and it increases as the impurity concentration of thesubstrate increases. Accordingly, V_(th) can be increased by increasingthe impurity concentration of the substrate.

Thus, when it is desired to raise the operation voltage, a voltageapplied to a wiring layer extending over the field oxidation region alsorises, resulting in a parastic channel immediately beneath the fieldoxide layer region. That is, a parastic MOS FET is formed. In order toavoid the formation of such a parastic MOS FET, it is necessary toincrease the impurity concentration of the substrate or the impurityconcentration of the well layer as seen from the above equation to raisethe threshold voltage V_(th) of the parastic MOS FET. However, since theimpurity concentrations of the substrate and the well layer aredetermined by electrical characteristics of the CMIS FET's such as thethreshold voltage V_(th) and mutual conductance gm, the range of theoperating voltage for the CMIS FET's is limited and the magnitudethereof is very small. For example, when the threshold voltage V_(th) ofan N-channel MOS FET formed in a P-type well layer is 0.45 volts, aparastic channel is formed at about 4 volts because an N-type inversionlayer is readily formed because of many sodium (+) ions present in thefield oxide layer. As a result, the operating voltage should be up toabout 3 volts.

As a commonly used method for manufacturing the CMIS FET's of the LOCOSstructure which avoids the formation of the parastic channel in theP-type well layer and which can be practiced in a simple way, atechnique disclosed in the Philips Technical Review, Vol. 34, No. 1,1974, pp. 19-23, is known. According to the technique disclosed therein,particularly in the right column on page 20 and FIG. 2 on page 21, theP-type well layer is formed by ion implantation technology after theformation of the LOCOS oxide (field oxide) layer. Therefore, while theparastic channel is not readily formed, a complex design of layout forthe MOS FET's and the wiring layers therefor is required when aplurality of MOS FET's are to be incorporated in the P-type well layerbecause LOCOS oxides cannot be formed in the P-type well layer. Theoperating voltage is also limited. That is, according to the disclosedtechnique, the operating supply voltage should be up to about 10 voltsbecause as the operating voltage rises, the area immediately beneath theLOCOS oxide formed in the semiconductor body is more apt to form aparastic channel by a wiring layer extending over the LOCOS oxide layeralthough the above area is made more N-type conductive by sodium (+)ions present in the LOCOS oxide. Furthermore, due to the thresholdvoltage V_(th) of the active region in the P-type well layer, it becomesimpossible to prevent the formation of the parastic channel in theP-type well as the operating voltage rises. Accordingly, the field ofapplication of the semiconductor integrated circuit device manufacturedby the disclosed technique is limited.

On the other hand, the field of application of the semiconductorintegrated circuit device comprising CMIS FET's is wide in these daysand, actually, the operating voltage therefor varies widely depending onthe specification of a particular product. It is, therefor, required tomanufacture CMIS FET's applicable to a variety of products of variousspecifications in a common process and provide (CMIS FET's which aresatisfactorily operable with a wide range of operating voltages. To thisend, a method for manufacturing CMIS FET's which can control thethreshold voltage V_(th) of the active region of the CMIS FET's and thethreshold voltage V_(th) of the parastic MOS FET to predeterminedvoltages is required.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method formanufacturing CMIS FET's of LOCOS structure which allows theestablishment of the threshold voltage V_(th) of the parastic MOS FET inthe field oxide layer region independently of the threshold voltageV_(th) of the active region whereby the operating voltage can be raisedand the range thereof can be widened.

It is another object of the present invention to provide a method formanufacturing CMIS FET's of LOCOS structure suited for a semiconductorintegrated circuit device comprising a number of CMIS FET's of LOCOSstructure.

It is another object of the present invention to provide a method formanufacturing CMIS FET's of LOCOS structure suited for a semiconductorintegrated circuit device operating at a high supply voltage.

It is another object of the present invention to provide a method formanufacturing CMIS FET's of LOCOS structure having less crystal defects.

It is another object of the present invention to provide a method formanufacturing CMIS FET's of LOCOS structure which allows a highintegration density.

It is another object of the present invention to provide a method formanufacturing CMIS FET's of LOCOS structure which is less influenced bycontamination.

In order to achieve the above objects, the method of manufacturing theCMIS FET's of the LOCOS structure according to the present inventioncomprises the following steps of:

(1) forming a P(or N)-type well layer in a portion of an N(or P)-typesemiconductor substrate surface and then forming a thin thermaloxidation layer over the entire surface and then forming a siliconnitride layer over the entire surface thereof,

(2) etching away the silicon nitride layer at areas on which field oxidelayers are to be formed,

(3) ion implanting donor (or acceptor) and acceptor (or donor)impurities at those areas in the N(or P)-type semiconductor substrateand the P(or N)-type well layer on which the field oxide layers are tobe formed,

(4) heat treating the substrate to selectively thermally oxidize theareas on which the field oxide layers are to be formed, using saidsilicon nitride layer as a mask, and

(5) removing the silicon nitride layer formed in the step (1) and thethin thermal oxidation film beneath the silicon nitride layer and thenforming a gate insulation layer, a source region and a drain region of.[.a.]. .Iadd.an .Iaddend.MIS device in the N(or P)-type semiconductorsubstrate and the P(or N)-type well layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 6 show one embodiment of the present inventionillustrating a sequence of steps, in partial sectional views, ofmanufacturing a semiconductor integrated circuit device comprising aplurality of CMIS FET's of LOCOS structure.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The method for manufacturing a CMIS FET IC of LOCOS structure of thepresent invention is now explained in the order of manufacturing steps.

(a) A portion of a surface of an N-type silicon substrate is delimited,in which a P-type well layer 2 of a thickness of about 6-8 μm is formedby ion implantation technique. Thereafter, the surface of the substrateis thermally oxidized in a dry O₂ atmosphere at about 1000° C. to form asilicon oxide (SiO₂) layer 3 of the thickness of about 700 A. Then, asilicon nitride (Si₃ N₄) layer 4 of the thickness of about 1000 A-1400 Ais formed by vapor reaction on the layer 3. (FIG. 1)

(b) The Si₃ N₄ layer 4 and the SiO₂ layer 3 therebeneath are etched awayexcept at areas 4a and 4b .[.on which field oxide layers are to beformed.]., using a photoresist layer 5 (5a and 5b) as a mask. Then, thatportion of the surface of the substrate 1 on which a P-channel MOSdevice is to be formed is covered with a photoresist layer 6, and thenboron (B) impurity 7 is ion implanted at 75KeV at that area of thesurface of the substrate 1 on which the field oxide layer of theN-channel MOS device is to be formed, using, as a mask, a photoresistlayer 6 and the photoresist layer 5a which has been used in etching theSi₃ N₄ layer 4 and the underlying SiO₂ layer 3 that a surface impurityconcentration of about 2×10¹³ atoms/cm² to 5×10¹³ atoms/ cm² is obtainedat the said area. (FIG. 2)

(c) After removing the photoresist layers 5 and 6, a new.[.photoresists.]. photoresist layer 8 is selectively formed on thatportion of the surface of the substrate 1 in which the N-channel MOSdevice is to be formed. Then, using the selectively formed photoresistlayer 8 and the silicon nitride (Si₃ N₄) layer under which the P-channelMOS device is to be formed as a mask, phosphorus (P) impurity 9 is ionimplanted at .Badd.45KeV in that portion of the surface of the substrate1 on which the field oxide layer of the P-channel MOS device is to beformed. (FIG. 3) The ion implantation energy of 45KeV for the phosphorusimpurity is enough to obtain an area of a sufficiently high surfaceimpurity concentration. On the other hand, with the acceleration energyof below 60KeV, phosphorus ions can be masked only by the Si₃ N₄ layeror the SiO₂ layer. Accordingly, the photoresist layer need not bemaintained on the Si₃ N₄ layer 4b. This means that the alignment of themask used in exposing step for the photoresist layer 8 need not behighly accurate. That is, an edge 8S of the photoresist layer 8 mayextend beyond a PN junction J between the P-type well layer 2 and theN-type substrate 1.

(d) After removing the photoresist layer 8, the substrate 1 is oxidizedin a wet oxygen atmosphere at 1000° C. for about 7.5 hours to form.Iadd.a .Iaddend.selective silicon oxide (SiO₂).[.layers.]. .Iadd.layer.Iaddend.10 of a thickness of about 1.4 μm of LOCOS structure (FIG. 4).In this case, because of the masking action of the Si₃ N₄ layer 4 to theoxygen, silicon oxide (SiO₄) layer is not formed on the areas coveredwith the Si₃ N₄ layer 4. Then, the selective oxidation mask of the Si₃N₄ layer 4 and the underlying thin SiO₂ layer 3 are removed (FIG. 4).

Through the heat treatment for forming the thick SiO₂ .[.layers.]..Iadd.layer .Iaddend.10 of the LOCOS structure, the impurities whichhave been ion implanted in the previous step are activated and diffusedso that P⁺ -type field diffusion .[.layers.]. .Iadd.layer .Iaddend.7aand N⁺ -type field diffusion .[.layers.]. .Iadd.layer .Iaddend.9a, whichact as parastic channel stopper layers, are formed (FIG. 4).

(e) On the surface of the substrate 1, gate oxide layers 11 of athickness of about 1000 A are formed in a dry O₂ atmosphere at 1000° C.Then, on the surfaces of the gate oxide layers 11, .Iadd.a.Iaddend.polycrystalline silicon .[.layers.]. .Iadd.layer .Iaddend.12.[.are.]. .Iadd.is .Iaddend. deposited to a thickness of about 3500 A.the polycrystalline silicon .[.layers are.]. .Iadd.layer is.Iaddend.then etched away by photoetching except those areas which areto act as gate electrodes .Iadd.12.Iaddend.. Etching is again carriedout using the remaining polycrystalline silicon layers 12 as a mask toremove the gate oxide layers 11 on the source and drain regions. Thedrain regions 13, 14 and the source regions 13a, 14a of the MOS devicesare then formed using the thick field oxide layers 10 and thepolycrystalline silicon layers 12 as a mask (FIG. 5).

The formation of the drain regions 13, 14.[.a .]. and the source regions13a, 14.Iadd.a .Iaddend.of the P-channel and N-channel MOS devices,respectively, is explained in more detail. A photoresist layer is formedon an area in which the N-channel MOS device is to be formed. Thoseportions of the gate oxide layer 11 which correspond to the source anddrain regions of the P-channel MOS device are removed. Then,.[.phosphorus.]. .Iadd.boron .Iaddend.impurity is diffused in theexposed surface of the substrate 1 using the polycrystalline siliconlayer 12 for the gate electrode G₁ and portions of the field oxide.[.layers.]. .Iadd.layer .Iaddend.10 as a diffusion mask, to form thesource region 14.Iadd.a .Iaddend.and the drain region 14.[.a.].. In thismanner, the P-channel MOS device is formed. Then, the photoresist layeris removed and new photoresist .[.layers are.]. .Iadd.layer is.Iaddend.formed on the source region 14.Iadd.a .Iaddend.and the drainregion 14.[.a.]. and the portions of the gate oxide layer 11 whichcorrespond to the source and drain regions of the N-channel MOS deviceare removed. Thereafter, using the polycrystalline silicon layer 12 forthe gate electrode G₂ of the .[.P.]. .Iadd.NP.Iaddend.-channel MOSdevice and the portions of the field oxide layer 10 as a diffusion mask,.[.boron.]. .Iadd.phosphorus .Iaddend.impurity is diffused to form thesource region 13a and the drain region 13.

(f) To insulate the polycrystalline silicon layers 12 for the gates.[.G.]. .Iadd.G₁ and G₂ .Iaddend., a silicon oxide (SiO₂) layer 15 isdeposited on the surface of the substrate by thermal decomposition ofsilane (SiH₄) (FIG. 6). A PSG (phosphosilicate glass) layer ispreferable as an insulating layer to insulate the polycrystallinesilicon layers 12 for the gate electrodes .[.G.]. .Iadd.G₁ and G₂.Iaddend.. Then, after forming windows for contacts, an aluminum layerof a thickness of 1 μm is formed by vacuum deposition and requiredaluminum wiring patterns as well as source electrodes S and drainelectrodes D are formed by a conventional photoetching process (FIG. 6).

(g) The wafer treatment process is thus completed. Thereafter it issliced into chips in a conventional manner, and they are assembled intodevices.

The present method for manufacturing the CMIS FET's of the LOCOSstructure described hereinabove has the following features.

(1) Since the field diffusion layers 7a and 9a having impurityconcentrations higher than that of the substrate 1 or the P-type welllayer 2 and selected independently of those impurity concentrations areformed under the thick SiO₂ layer 10 which act as the field oxide layer,the threshold voltage V_(th) of the parastic MOS transistor in theregion of the field oxide layer 10 can be controlled to any value byadjusting the amount of ion implantation, and it can be setindependently of the threshold voltages V_(th) of the substrate 1 andthe P-type well layer 2. Therefore, according to the present invention,it is possible to manufacture CMIS FET's and semiconductor integratedcircuit devices comprising a number of CMIS FET's having differenceoperating voltages in the same manufacturing process.

(2) In the formation of the field diffusion layers 7a and 9a, the Si₃ N₄layer 4 which serves as the mask in forming the thick field siliconoxide layer 10 by the thermal oxidation is used in situ. Therefore, thefield diffusion layers 7a and 9a are self-aligned with the field siliconoxide layer 10 and the sources and drains of the devices resulting in ahigh integration density. Thus, the semiconductor device of the presentinvention can be manufactured in a very simple way.

(3) Because of the CMIS semiconductor device of the LOCOS structure,fine processing is possible. Furthermore the performance of the deviceis high in that it provides a high operation speed and a low powerconsumption. Therefore, the CMIS FET's of the present invention can beapplied to various products.

(4) Since the P-type well layer is formed before the formation of thefield oxide layer, it is possible to form the field oxide layer in thewell layer. Thus, when it is desired to form a plurality of MOS FET's inthe well layer, the design of the layouts of the MOS FET's and thewiring layers therefor is facilitated. Furthermore, the source and drainregions can be readily formed using the field oxide .[.layers.]..Iadd.layer .Iaddend.in the well layer as the mask.

In ion implanting the impurity in the above embodiment, the thin SiO₂layer 3 under the Si₃ N₄ layer 4 is removed to expose the surfaces ofthe N-type substrate 1 and the P-type well layer 2. However, the thinSiO₂ layer 3 may be left unremoved. In this case, less defects on thesurfaces of the N-type substrate 1 and the P-type well layer 2 due tothe ion damage take place and the affect by the contamination isminimized because the surfaces are not exposed. Furthermore, by thepresence of the thin SiO₂ layer 3, bird-beaks do not grow. That is, whenthe thin SiO₂ layer 3 is etched away, the parts of the SiO₂ layer 3under the Si₃ N₄ layers 4a and 4b, which are called overhung, are alsoetched away. As a result, lateral oxidation proceeds more rapidlyresulting in the growth of the bird-beaks. On the other hand, when thethin SiO₂ layer 3 is left unremoved, the bird-beaks are grown lessslowly so that the area occupied by the field oxide layers is minimizedresulting in the increase in the integration density.

In the above embodiment, the parastic channel stopper layers (fielddiffusionlayers) are formed under the field oxide layers formed in theP-type well layer and the substrate. In this case, the operating voltageof up to about 50 volts is permitted. On the other hand, if thesemiconductor integrated circuit device manufactured by the presentmethod is to be used at the operating voltage of less than 10 volts, thephosphorus ion implantation shown in FIG. 3 may be omitted, because ifthe V_(th) of the P-channel MOS FET is 0.45 volts the V_(th) of theN-type parastic channel is as high as 12 volts or higher and it is notreadily inverted at the opening voltage of below 10 volts.

It should be understood that the present invention is not limited to theembodiment described above but it can be applied to the CMIS FET's ofthe LOCOS structure having various gate electrodes or gate insulationlayers and the semiconductor integrated circuit devices comprising suchCMIS FET's.

We claim:
 1. A method for manufacturing complementary insulated gatefield effect transistors comprising the steps of:(a) delimiting aportion of a surface of a semiconductor substrate of a firstconductivity type and forming therein a well layer of a secondconductivity type, forming a thin insulating layer over the entiresurface thereof and then forming a silicon nitride layer over the entiresurface thereof; (b) etching away said silicon nitride layer at least.[.those areas on.]. .Iadd.in an area in .Iaddend.which a field oxide.[.layers are.]. .Iadd.layer is .Iaddend.to be formed; (c) introducing.Iadd.an .Iaddend.impurity of the second conductivity type at that areain said well layer of the second conductivity type on which the fieldoxide layer is to be formed; (d) heat treating the substrate toselectively thermally oxidize the areas on which the field oxide.[.layers are.]. .Iadd.layer is .Iaddend.to be formed, using saidsilicon nitride layer as a mask to form a thick field oxide layer; and(e) removing the silicon nitride layer and the underlying thininsulating layer formed in said step (a), selectively forming gateinsulation layers and silicon layers on the exposed substrate and welllayer, .Iadd.and .Iaddend.forming source regions and drain regions of.[.MIS devices.]. .Iadd.insulated gate field effect transistors.Iaddend.in said semiconductor substrate of the first conductivity typeand the well layer of the second conductivity type using said siliconlayers and said thick field oxide .[.layers.]. .Iadd.layer .Iaddend.asmasks.[., and forming diffusion layers of desired impurityconcentrations beneath said thick field oxide layers.]..
 2. A method formanufacturing complementary insulated gate field effect transistorsaccording to claim 1 wherein said step (b) includes a sub-step ofetching away the thin insulating layer under the .[.siliocn.]..Iadd.silicon .Iaddend.nitride layer.
 3. A method for manufacturingcomplementary insulated gate field effect transistors according to claim2 wherein said thin insulating layer is a thermal oxidation layer.
 4. Amethod for manufacturing complementary insulated gate field effecttransistors according to claim 1 wherein in said step (c) said impurityof the second conductivity type is introduced, by ion implantation, intothose areas of the well layer of the second conductivity type on whichthe field oxide .[.layers are.]. .Iadd.layer is .Iaddend.to be formed.5. A method for manufacturing complementary insulated gate field effecttransistors comprising the steps of:(a) delimiting a portion of asurface of an N-type semiconductor substrate and forming a P-type welllayer therein, forming a thin thermal oxidation layer over the surfacethereof and then forming a silicon nitride .[.film.]. .Iadd.layer.Iaddend.over the surface thereof; (b) etching away said silicon nitridelayer at those areas on which a field oxide .[.layers are.]. .Iadd.layeris .Iaddend.to be formed; (c) ion implanting donor and acceptorimpurities into those areas in said N-type semiconductor substrate andthe P-type well layer, respectively, on which the field oxide .[.layersare.]. .Iadd.layer is .Iaddend.to be formed, using a portion of saidsilicon nitride layer as a mask; (d) heat treating the substrate toselectively thermally oxidize those areas on which the field oxide.[.layers are.]. .Iadd.layer is .Iaddend.to be formed, using saidsilicon nitride layer as a mask for forming the field oxide .[.layers.]..Iadd.layer .Iaddend.of LOCOS structure; and (e) removing said siliconnitride layer and the underlying thin thermal oxidation layer formed insaid step (a), selectively forming gate insulation layers andsemiconductor layers on the exposed N-type substrate and exposed P-typewell layer, forming source regions and drain regions of .[.MISdevices.]. .Iadd.insulated gate field effect transistors .Iaddend.insaid N-type semiconductor substrate and said P-type well layer usingsaid semiconductor layers and said field oxide .[.layers.]. .Iadd.layer.Iaddend.as masks.
 6. A method for manufacturing complementary insulatedgate field effect transistors according to claim 5 wherein in said step(c) the donor is phosphorus and the acceptor is boron.
 7. A method formanufacturing complementary insulated gate field effect transistorscomprising the steps of:(a) delimiting a portion of a surface of anN(P)-type semiconductor substrate and forming a P(N)-type well layertherein, forming a thin thermal oxidation layer over the entire surfacethereon, and then forming a silicon nitride layer over the entiresurface thereof; (b) etching away said silicon nitride layer and theunderlying thin thermal oxidation layer at those areas on which .Iadd.a.Iaddend.field oxide .[.layers are.]. .Iadd.layer is .Iaddend.to beformed; (c) ion implanting .[.acceptor (donor) or.]. donor (acceptor)impurity in the exposed surface area of the substrate .[.in the area ofN(P) channel of P(N) channel device.].; (d) ion implanting .[.donor(acceptor) or.]. acceptor (donor) impurity in the exposed surface area.[.of the substrate in the area of P(N) channel of N(P)channel device.]..Iadd.of the well layer.Iaddend.; (e) heat treating the substrate toselectively thermally oxidize the exposed surface areas of the substrate.Iadd.and the well layer .Iaddend.using said silicon nitride layer as amask to form .Iadd.a .Iaddend.thick field oxide .[.layers.]..Iadd.layer.Iaddend.; and (f) removing the silicon nitride layer and theunderlying thin thermal oxidation layer formed in the step (a),selectively forming gate insulation layers and silicon layers on theexposed surface area of the substrate and well layer, .Iadd.and.Iaddend.forming source regions and drain regions of the respective.[.MIS devices.]. .Iadd.insulated gate field effect transistors.Iaddend.using said silicon layers and said thick field oxide.[.layers.]. .Iadd.layer .Iaddend.as masks.[., and forming diffusionlayers of desired impurity concentrations under said field oxidelayers.]..
 8. A method for manufacturing a semiconductor integratedcircuit device including complementary insulated gate field effecttransistors comprising the steps of:(a) delimiting a portion of asurface of an N-type silicon substrate and forming a P-type well layertherein by ion implantation, forming a silicon dioxide layer over theentire surface thereof and then forming a silicon nitride layer over theentire surface thereof; (b) selectively forming a first photoresistlayer on said silicon nitride layer over said N-type silicon substrateand said P-type well layer; (c) etching away said silicon nitride layerand the underlying silicon .[.nitride.]. .Iadd.dioxide .Iaddend.layerusing said first photoresist layer as a mask to expose surfaces of saidN-type silicon substrate and said P-type well layer; (d) covering theexposed N-type silicon substrate surface with a second photoresistlayer; (e) ion implanting an acceptor impurity into the exposed surfacearea of said P-type well layer using said first photoresist layer as amask; (f) removing said first and second photoresist layers and coveringthe exposed surface of said P-type well layer with a third photoresistlayer; (g) ion implanting a donor impurity into the exposed surface areaof said N-type silicon substrate using said silicon nitride as mask; (h)removing said third photoresist film and selectively thermally oxidizingthe exposed surfaces of said P-type well layer and said N-type siliconsubstrate using said silicon nitride layer as a a mask to form .Iadd.a.Iaddend.thick field silicon dioxide .[.layers.]. .Iadd.layer.Iaddend.;(i) etching away said silicon nitride layer and the underlying silicondioxide layer to expose said P-type well layer and said N-type siliconsubstrate; (j) oxidizing the exposed surfaces of said P-type well layerand said N-type silicon substrate to form gate silicon dioxide layers;(k) forming .Iadd.a .Iaddend.silicon .[.layers.]. .Iadd.layer.Iaddend.over .Iadd.the .Iaddend.entire surfaces of said field silicondioxide .[.layers.]. .Iadd.layer .Iaddend.and said gate silicon dioxidelayers; (l) selectively etching away said silicon .[.layers.]..Iadd.layer .Iaddend.and said gate silicon dioxide layers to expose thesurfaces of said N-type silicon substrate and said P-type well layer;(m) diffusing an acceptor impurity into the exposed N-type siliconsubstrate and a donor impurity into the exposed P-type well layer usingthe remaining silicon layer and said field silicon dioxide .[.layers.]..Iadd.layer .Iaddend.as masks to form source regions and drain regions,respectively, and (n) connecting aluminum layers to said source regionsand drain regions formed in said N-type silicon substrate and saidP-type well layer, respectively. .Iadd.
 9. A method for manufacturing asemiconductor device including insulated gate field effect transistors,comprising the steps of:(a) forming a silicon substrate containing awell region of one conductivity type extending to a major surface of thesubstrate, and a substrate region of another conductivity type adjoiningsaid well region and extending to said major surface; (b) covering saidmajor surface of the substrate with an oxidation-resistive material tocover selected surface areas of said well and substrate regions andleave other surface area portions of said well and substrate regionsuncovered with said oxidation-resistive material; (c) introducing afirst impurity determining said one conductivity type into the uncoveredsurface area portions of said well region; (d) subjecting thecombination thus obtained to an oxidation treatment to selectivelyoxidize portions of said substrate which are not covered with saidoxidation-resistive material thereby to form a relatively thick siliconoxide layer having a plurality of openings at said selected surfaceareas; (e) removing said oxidation-resistive material from saidsubstrate; (f) forming relatively thin silicon oxide layers on saidselected surface areas in said openings; and (g) forming at saidselected surface areas in said openings insulated gate field effecttransistors using said relatively thin silicon oxide layers as gateinsulators. .Iaddend. .Iadd.
 10. The method of claim 5 or 7, wherein theheat treating of the substrate is performed at a temperature sufficientto form diffusion layers of desired impurity concentrations beneath saidthick field oxide layer. .Iaddend. .Iadd.
 11. The method of claim 1,wherein, in step (b), the silicon nitride layer is etched withoutetching away the thin insulating layer, whereby steps (c) and (d) areperformed without exposure of the substrate and well layer..Iaddend..Iadd.
 12. The method of claim 5, wherein, in step (b), thesilicon nitride layer is etched without etching away the thin thermaloxidation layer, whereby steps (c) and (d) are performed withoutexposure of the substrate and well layer. .Iaddend. .Iadd.
 13. Themethod of claim 8, wherein the selectively thermally oxidizing theexposed surfaces of the P-type well layer and the N-type siliconsubstrate is performed at a temperature sufficient to form diffusionlayers of desired impurity concentrations beneath the thick fieldsilicon dioxide layer. .Iaddend. .Iadd.
 14. The method of claim 9,wherein said oxidation-resistive material is silicon nitride. .Iaddend..Iadd.
 15. The method of claim 9, further comprising the steps of:(c1)introducing a second impurity determining said other conductivity typeinto the uncovered surface area portions of said substrate regionbetween the step (b) and the step (d); (d1) then carrying out said step(d) thereby to form channel stopper regions underneath said relativelythick silicon oxide layer. .Iaddend..Iadd.
 16. The method of claim 15,wherein said first impurity is introduced by ion implantation whilecovering the openings other than those reaching said well region with aphotoresist material, and said second impurity is introduced by ionimplantation while covering the openings other than those reaching saidsubstrate region with a photoresist material. .Iaddend. .Iadd.
 17. Amethod for manufacturing a semiconductor integrated circuit deviceincluding circuit elements, comprising the steps of: (a) forming asilicon substrate containing a well region of one conductivity typeextending to a major surface of the substrate and a substrate region ofanother conductivity type adjoining said well region and extending tosaid major surface; (b) covering said major surface of the substratewith an oxidation-resistive mask, said mask having a plurality ofislands of an oxidation-resistive material which cover the surface ofsaid well region other than selected surface areas in the midst, as wellas in the periphery, of the surface of the well region; (c) introducingan impurity determining said one conductivity type into the selectedsurface areas of said well region; (d) subjecting the combination thusobtained to an oxidation treatment to selectively oxidize portions ofsaid major surface of the silicon substrate which are not covered withsaid mask, thereby to form a relatively thick silicon oxide layer whichincludes a plurality of first openings located at portions of said wellregion corresponding to said islands of said oxidation-resistivematerial and second openings located on the surface of said substrateregion; (e) removing said oxidation-resistive mask from the majorsurface of said substrate; (f) forming relatively thin silicon oxidelayers covering the surface portions of said well and substrate regionsat said first and second openings; and (g) forming circuit elements atsurface portions of said well and substrate regions in said first andsecond openings. .Iaddend. .Iadd.
 18. The method of claim 17, whereinsaid oxidation-resistive material comprises silicon nitride..Iaddend..Iadd.
 19. The method of claim 17 or 18, wherein said circuitelements are insulated gate field effect transistors. .Iaddend..Iadd.20. A method for manufacturing a semiconductor device includinginsulated gate field effect transistors, comprising the steps of:(a)forming a silicon substrate containing a well region of one conductivitytype extending to a major surface of the substrate, and a substrateregion of another conductivity type adjoining said well region,underlying said well region and extending to said major surface; (b)covering said major surface of the substrate with an oxidation-resistivematerial to cover selected areas of said well and substrate regions; (c)introducing an impurity determining said other conductivity type intothe selected surface areas of said substrate region; (d) subjecting thecombination thus obtained to an oxidation treatment to selectivelyoxidize portions of said substrate and well regions which are notcovered with said oxidation-resistive material so as to form arelatively thick silicon oxide layer having a plurality of openings atsaid selected surface areas and so as not to reach portions of saidsubstrate region underlying said well region; (e) removing saidoxidation-resistive material from said substrate; (f) forming relativelythin silicon oxide layers on said selected surface areas in saidopenings; and (g) forming at said selected surface areas in saidopenings insulated gate field effect transistors using said relativelythin silicon oxide layers as gate insulators. .Iaddend. .Iadd.
 21. Themethod of claim 9, 17 or 20, wherein said relatively thin silicon oxidelayers have a thickness of about 1000 A. .Iaddend. .Iadd.
 22. The methodof claim 9, 17 or 20, wherein said oxidation treatment is performed at atemperature of about 1000° C. .Iaddend. .Iadd.
 23. The method of claim22, wherein said relatively thin silicon oxide layers have a thicknessof about 1000 A. .Iaddend. .Iadd.
 24. The method of claim 22, whereinsaid relatively thick silicon oxide layer formed has a thickness ofabout 1.4 μm. .Iaddend. .Iadd.
 25. The method of claim 24, wherein saidrelatively thin silicon oxide layers have a thickness of about 1000 A..Iaddend. .Iadd.
 26. The method of claim 9, 17 or 20, wherein saidrelatively thick silicon oxide layer formed has a thickness of about 1.4μm. .Iaddend. .Iadd.
 27. The method of claim 26, wherein said relativelythin silicon oxide layers have a thickness of about 1000 A. .Iaddend..Iadd.
 28. The method of claim 9, 15, 16, 14 or 20, wherein prior tostep (b), said major surface of the substrate is covered with a thininsulating layer. .Iaddend..Iadd.
 29. The method of claim 28, whereinsaid thin insulating layer is a thermal oxidation layer. .Iaddend.